01｜Theoretically, yes, but the process is not recommended

First, let's look at two levels of considerations:
✅ Theory: Smaller lead inductance From the perspective of electrical performance, punching vias directly on pads can shorten the connection path and reduce lead inductance, which is particularly suitable for high-speed signals or high-frequency designs.

❌ Process: Poor welding is prone to "tombstone"! But in actual production, you will face a serious problem - tin leakage and tombstone phenomenon (Tombstone)!

Why does tombstone occur?

The via is punched on the pad. If the plug hole is not sealed
During welding, the solder paste flows out of the via under the action of hot air
The two sides are heated unevenly, and the light chip components "lift up on one side"

This phenomenon is called the "tombstone effect", also known as the "Manhattan phenomenon

02｜Recommended practice: pull out the pad and then punch!

In order to take into account both design performance and process reliability, we strongly recommend:

✅ Do not punch the via directly on the pad, but pull it out through the routing and then punch it.

This can control the lead inductance and avoid the problem of solder paste loss during welding!

Extended knowledge: Two keywords you should know

Parasitic Inductance

In high-frequency circuits, a section of wire or even a via will produce inductive reactance, which will have an adverse effect on signal integrity.
Therefore, the length and number of vias should be minimized in the design.

Tombstone

During the reflow process of chip components, due to uneven heating and unbalanced force of solder paste, one end of the device is lifted.

Influencing factors include:

Asymmetric pad area
Uneven solder paste coating
Via holes punched on pads cause tin leakage

The via pad design may seem like a detail, but it directly affects the soldering yield and electrical performance. A reasonable layout can avoid a lot of rework and quality control problems!